Usually, a gate driver circuit of a display device includes a plurality of shift register units connected in a cascaded manner, and the shift register unit at each level includes an pull-up node and an output end. In order to output a signal normally, it is necessary to reset the pull-up node and the output end after a scanning signal is outputted by a current-level shift register unit. In order to enhance a driving capability of the gate driver circuit and reduce a falling time, usually the pull-up node and the output end of each shift register unit are reset separately.
For the gate driver circuit, a resetting signal is applied by a next-level shift register unit to the current-level shift register unit, and the pull-up nodes and the output ends of the shift register units at the next levels are reset through a supplement resetting module. For the shift register units at the two adjacent levels, an output resetting end of a second-level shift register unit is usually connected to a pull-up node resetting end of a first-level shift register unit. In the case that the second-level shift register unit outputs a signal, a gate electrode (i.e., the output resetting end) of a pull-down transistor may be coupled to a high level due to the existence of a parasitic capacitance. Because the output resetting end of the second-level shift register unit is connected to the pull-up node resetting end of the first-level shift register unit, a potential at the pull-up node resetting end of the first-level shift register unit may be pulled up correspondingly. As a result, a leakage current may occur for the pull-up node of the first-level shift register unit.
Hence, in the case of resetting the current-level shift register unit, there is an urgent need to prevent the occurrence of leakage current for the pull-up node of the previous-level shift register unit.